Celero Communications
A 2nm coherent DSP platform for AI infrastructure — targeting the architectural gap between bandwidth-constrained PAM4 and over-engineered long-haul coherent, as scale-up, scale-out and scale-across topologies push connectivity past its physical limits
Data Integrity Notice: This analysis is compiled from Celero’s own disclosures and investor communications (BusinessWire, CapitalG, company blog) and secondary trade coverage (SiliconANGLE, Converge Digest, and others). Revenue, bookings, customer concentration and margin data are undisclosed. The $3B+ valuation is a self-reported figure from the round announcement, not derived from audited financial statements. Series A and Series B were disclosed jointly in November 2025 as a combined $140M; individual round sizes and interim valuations were not broken out. Readers should weight the analysis accordingly.
Celero Communications is a fabless semiconductor startup founded in 2024, developing coherent DSP (digital signal processor) silicon for AI infrastructure connectivity. The company is headquartered in Irvine, California, with additional design centers in Canada and Argentina — a three-site R&D footprint for a company barely two years old. The more relevant underwriting fact, however, is that the founding team is less a startup than a reconstituted veteran bench from the coherent DSP industry’s prior consolidation cycle.
A founding member of Broadcom, Yousefi went on to serve as CEO of ClariPhy Communications, a coherent DSP company later acquired by Inphi. Following the acquisition, he ran the Switch, Automotive and Coherent DSP businesses as an EVP at Inphi, and then continued in that role after Marvell’s acquisition of Inphi. That progression — founding a coherent DSP company, taking it through an acquisition, then running the resulting business unit inside a much larger fabless platform — gives him a full-cycle operating record that few first-time semiconductor founders can claim. From an underwriting standpoint, this is the single strongest data point in the deal: a CEO who has already built, sold and scaled the exact category he is now re-entering.
Former CTO and SVP at ClariPhy, and subsequently a senior design leader at Inphi and Marvell, Agazzi is regarded as one of the industry’s most accomplished DSP architects. His partnership with Yousefi predates Celero by more than a decade, which meaningfully reduces founder-pair continuity risk relative to a typical newly-formed team.
The company states its ~100-person (and growing) team draws heavily from engineers who shipped some of the industry’s highest-volume DSPs at Marvell, Inphi and Broadcom. This is a company-reported claim; no independently verified headcount breakdown or org chart has been published.
Celero’s core asset is the 2nm coherent DSP silicon it announced validating in September 2026. The company characterizes this as the industry’s first 2nm coherent DSP incorporating advanced analog technology, and describes a scalable architecture path from current-generation 1.6T solutions to next-generation 3.2T AI optical interconnects. The “industry first” framing is company-sourced; no independent benchmarking or third-party silicon validation has been made public, and analysts should treat the claim as unverified marketing language pending customer proof points.
A single 2nm die integrating DSP processing with advanced analog technology, targeting high-speed, low-power coherent transmission to improve fiber efficiency and support higher-capacity networking platforms. Celero positions this as a full process-node ahead of Broadcom’s 3nm Taurus BCM83640 optical DSP, announced in March 2026.
Coherent architecture aimed at the 1.6T bandwidth tier currently being deployed across hyperscale AI clusters and cloud data centers. Celero calls this the industry’s first scalable coherent architecture at this tier; volume production status and named customer adoption remain undisclosed.
A forward roadmap addressing scale-up, scale-out and scale-across AI network connectivity at 3.2T. Management has indicated new capital will be prioritized toward accelerating this roadmap and building out production readiness.
Market context (third-party TAM estimate, not company-specific): McKinsey projects global data centers will require nearly $7 trillion in investment by 2030, of which roughly $5.2 trillion is tied to AI workloads. The core round thesis is that networking is now growing faster than compute, making optical interconnect a critical bottleneck — but this is a macro TAM figure, not a reflection of Celero’s own pipeline, bookings or revenue, and should not be conflated with company-level demand signals.
Competitive positioning summary: Celero’s underlying bet is that traditional PAM4/IMDD architectures are approaching real physical limits on bandwidth density and fiber scalability, and that coherent technology becomes the default interconnect standard for scale-up, scale-out and scale-across AI networks. This puts Celero in direct contention with Marvell and Broadcom, both of which are extending coherent-lite and high-performance PAM DSP lines into the same campus-scale data center interconnect segment Celero is targeting.
Celero has raised a cumulative $415M in just under two years of operation, reaching a valuation above $3 billion. Notably, the Series C round size roughly doubled the combined Series A/B raise just ten months after the earlier round closed — a strong signal of institutional conviction in the AI infrastructure optical interconnect thesis. That said, interim valuation marks (particularly at the Series A/B stage) were never disclosed, which makes it impossible to compute a clean step-up multiple across rounds.
Nariman Yousefi and Oscar Agazzi incorporated Celero on the back of a partnership dating to their ClariPhy, Inphi and Marvell years. Initial funding size and timing were not disclosed in public sources; the company appears to have operated largely in stealth through its first raise announcement in November 2025.
A Series A led by Sutter Hill Ventures and a Series B led by CapitalG (Alphabet’s independent growth fund) were disclosed together, with Valor Equity Partners, Atreides Management and Maverick Silicon participating across the two rounds. Individual round sizes and valuations were not broken out — a transparency limitation analysts should factor into any step-up calculation. CapitalG partner James Luo joined the board.
Announced alongside the 2nm coherent DSP silicon validation, this round was co-led by Atreides Management, Valor Equity Partners and CapitalG, with continued participation from existing investors Sutter Hill Ventures and Maverick Silicon. Atreides Managing Partner and CIO Gavin Baker joined the board — a governance-level commitment beyond capital deployment. The round pushed Celero’s valuation above $3 billion.
The investment case for Celero rests on four pillars: (1) a founding team with genuine full-cycle execution history in coherent DSP, (2) architectural positioning in the underserved gap between PAM4 and legacy long-haul coherent, (3) a claimed process-node lead via 2nm silicon, and (4) repeat validation from top-tier crossover and strategic investors. This remains, however, a pre-revenue moat that has not yet converted into volume shipments or disclosed design wins — a distinction that warrants a more conservative read than the headline valuation implies.
CEO Nariman Yousefi’s arc runs from Broadcom founding member, through founding and selling ClariPhy (a coherent DSP company) to Inphi, to running the Switch, Automotive and Coherent DSP business units at Inphi and then Marvell post-acquisition. CTO Oscar Agazzi has run the identical trajectory alongside him. This is an unusually complete operating pedigree for an early-stage fabless company, and it should shorten both team-building cycles and enterprise sales cycles with hyperscale customers who already know this team’s prior products.
Legacy telecom-grade coherent DSPs carry cost and power penalties that make little sense at AI-data-center distances, while PAM4/IMDD faces hard physical ceilings on bandwidth density and reach. Celero is targeting the middle ground — campus-scale scale-up, scale-out and scale-across connectivity. This segment materially overlaps with Marvell’s own coherent-lite roadmap, so durability of the differentiation will ultimately be determined by actual design wins, not architecture alone.
Where Broadcom’s March 2026 Taurus BCM83640 optical DSP shipped on a 3nm monolithic process, Celero claims validation of a 2nm coherent DSP — a leading-edge process image versus the two large incumbents. This is a company-disclosed claim only; there is no independent verification of yield, cost competitiveness, or production timeline, and leading-edge nodes inherently carry greater foundry-allocation and yield-ramp risk.
CapitalG (Alphabet’s growth fund) and Atreides Management (CIO Gavin Baker now on the board) have led back-to-back rounds, with Valor Equity Partners, Sutter Hill Ventures and Maverick Silicon providing continuity as specialist semiconductor and deep-tech investors. In a capital-intensive, leading-edge semiconductor business, access to repeat institutional capital is itself a competitive asset — though whether CapitalG’s Alphabet affiliation translates into an actual commercial relationship (e.g., Google infrastructure adoption) has not been confirmed.
From a buy-side underwriting lens, Celero presents a classic “proven team, unproven commercialization” profile typical of early-stage deep-tech semiconductor deals. The following factors are central to assessing whether the $3B+ valuation is durable.
The 2nm process has been “validated,” not brought to volume production. Leading-edge nodes carry structurally elevated yield instability, foundry-capacity competition and cost-structure risk, and the path from validated silicon to revenue typically requires significant additional time and capital.
Marvell and Broadcom already run large-scale PAM/coherent-lite DSP businesses, and both Ciena (via its Nubis Communications acquisition) and Marvell (via its Celestial AI acquisition) have shown a clear pattern of absorbing promising interconnect startups rather than competing head-on. Whether Celero remains independent or becomes an acquisition target itself is an open question that bears directly on whether the current valuation is ultimately justified.
Revenue, backlog, customer concentration and gross margin are entirely undisclosed. It is not possible to derive what revenue multiple underlies the $3B+ valuation, suggesting the pricing is driven largely by technology roadmap and investor conviction rather than demonstrated financial performance.
Celero’s addressable market thesis depends heavily on continued hyperscaler AI data center capex growth. McKinsey’s $7 trillion figure is a macro estimate, not a company-specific demand signal, and any slowdown or correction in AI infrastructure investment would directly compress demand for the campus-scale interconnect capacity Celero is targeting.
Bottom line: Celero combines one of the strongest founding-team pedigrees available in coherent DSP with a coherent and differentiated architectural thesis, making it an attractive risk-reward profile within early-stage deep-tech semiconductors. That said, the $3B+ valuation is priced off a roadmap that has not yet been commercially validated. The key re-rating trigger over the next 12–24 months will be whether Celero converts its process-node claims into disclosed design wins, production volume and revenue visibility.